This paper presents the design and simulation of a low-power full-band UWB transmitter with on-chip
quadrature voltage-controlled oscillator (QVCO) in 130 nm CMOS technology. The proposed transmitter
consists of a passive poly-phase filter (PPF), QVCO, a quadrature modulator core and an RF power
amplifier. The QVCO uses the differential delay cell architecture with four cascaded stages. The transmitter
has the following specifications: a 15.28 dB average conversion gain with a ripple of ±1dB from 2 GHz to 11
GHz, the average input 1-dB compression point (IP1dB) is ‒10 dBm and the average output 1-dB
compression point (OP1dB) is 4.35 dBm. The QVCO achieves a wide frequency range (2-11 GHz) with a ‒80
dBc/Hz phase noise. In addition, the supply voltage of the proposed transmitter is 1.2 V with power
consumption of 77.8 mW.
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